1. Field of the Invention
The present invention relates to a digital signal processing apparatus and, more particularly, to an apparatus for generating a signal whose phase is synchronized with a digital signal inputted.
2. Related Background Art
Hitherto, as such a kind of apparatus, there has been known a digital VTR for converting a video signal to a digital signal and for recording or reproducing the signal onto/from a magnetic tape.
FIG. 1 is a block diagram showing a construction of a reproducing system in such a digital VTR.
In FIG. 1, reference numeral 1 denotes a magnetic tape; 2 a magnetic head for recording or reproducing a signal to/from the magnetic tape 1; 3 a head amplifier for amplifying a reproduced signal of the magnetic head 1; 4 a reproduction equalizer which has predetermined frequency characteristics to equalize an output of the head amplifier 3 and which is constructed by an LC network and the like; 18 a data detection circuit for converting an output signal of the reproduction equalizer 4, namely, a signal whose amplitude is changed in an analog manner to a digital signal again; 20 a PLL circuit for generating a clock synchronized with an output of the data detection circuit 18; 19 a sample-hold circuit for sampling and holding an output of the data detection circuit 18 by the clock that is generated from the PLL circuit 20; 9 a demodulator for demodulating the data which was sampled and held; 10 an error correction decoding circuit for correcting errors by detecting errors included in the demodulated reproduced data by using parity data added upon recording; 11 a reproduced signal processing circuit for performing a signal process which is almost opposite to a signal process at the time of the recording to the error corrected data, thereby decoding an encoded video signal and extending an information amount; and 12 a D/A converter for converting the signal processed data to the analog signal.
The operation will now be described. The micro reproduced signal obtained from the magnetic head 2 by reproducing the magnetic tape 1 on which video image data has been recorded is amplified to 50 to 60 Db by the head amplifier 3.
The frequency characteristics of the reproduced signal amplitude of the magnetic head 2 frequency characteristics of a magnetic recording and reproducing system as shown in FIG. 2, they are differentiating characteristics in a low frequency band and are attenuating characteristic in a high frequency band due to various losses. In the reproduction equalizer 4, the characteristics of the magnetic recording and reproducing system are compensated by using characteristics shown in FIG. 3 which are opposite to those in FIG. 2, thereby correcting the above reproduced signal amplitude. Such a method is an equalizing method called an integrating method.
An output waveform of the reproduction equalizer 4 of the foregoing integrating method becomes an eye-pattern waveform as shown in FIG. 4. A waveform of such an eye-pattern is converted by using a comparator or the like in which a threshold level is selected at a position near the center by the data detection circuit 18, thereby deriving reproduced digital data.
The PLL circuit 20 generates a clock synchronized with the reproduced digital data. The sample-hold circuit 19 samples and holds the above reproduced digital data by using such a clock. The sampled and held data is demodulated by the demodulator 9. Further, errors of such demodulated data are corrected by the error correction decoding circuit 10 by using an error correction parity added at the time of the recording. In the reproduced signal processing circuit 11, a signal process which is almost opposite to the signal process upon recording of the data is executed. The processed signal is D/A converted by the D/A converter 12, thereby obtaining a reproduced video image signal.
In recent years, as an equalizing method of a reproduction equalizer which is used in a VTR for recording at a high density, a system using an inter-code interference of a reproduced waveform called a partial response system (PR method) is being developed.
In order to reduce reproduction errors, a technique in which such a system is combined with the Viterbi decoding method for detecting data by using a correlation of a reproduced signal in the direction of a time base is becoming a main stream nowadays.
FIG. 5 is a block diagram of a reproducing system of a digital VTR using a PR(1, -1) method and a Viterbi decoder among the above partial response methods.
In FIG. 5, reference numeral 5 denotes a delay circuit for delaying the output of the reproduction equalizer 4 by a time corresponding to one bit; 6 a subtracter for subtracting a delay output from the output of the reproduction equalizer 4; 7 an A/D converter for converting a subtraction output to digital data of a plurality of bits per one sample by the A/D conversion clock from the PLL circuit 20; and 8 a Viterbi decoder for converting the A/D conversion output to the digital data of one bit per one sample by using a Viterbi algorithm.
In this instance, an equalizer of the PR(1, -1) method is constructed by the 1-bit delay circuit 5 and subtracter 6. Transmission characteristics of a transmission path are characteristics for suppressing a low frequency component as shown in FIG. 6.
In recent years, a metal evaporation deposited tape (ME tape) has been being developed in order to record at a high density. According to the characteristics of the ME tape, a high frequency output is higher than that of a conventional metal painting type tape (MP tape) by a few dB, however, what is called a vertical component of residual magnetization is strong depending on a convenience in a manufacturing procedure. The low frequency component especially becomes a cause of a waveform distortion. To prevent such a distortion, the partial response method is used.
Subsequently, an output of the subtracter 6 is A/D converted by the A/D conversion clock obtained from the PLL circuit 20 by the A/D converter 7, thereby detecting data having few error by using a correlation in the direction of the time base of the reproduced signal by the Vitierbi decoder 8. The detected data is added to the demodulator 9 and subsequent processes are executed in a manner similar to those in FIG. 1. A detailed description with respect to the operation of the Viterbi decoder 8 is omitted here.
The partial response system as mentioned above is not limited to the PR(1, -1) method, but a PR(1, 0, -1) method is also considered.
A reproducing system of a digital VTR using the PR(1, 0, -1) method will now be described hereinbelow.
FIG. 7 is a block diagram showing a construction of the reproducing system of such a digital VTR. The construction up to the equalization of the reproduced signal by the reproduction equalizer 4 is substantially the same as that in FIG. 5.
In FIG. 7, the delay circuit 5 delays the digital signal from the A/D converter 7 by a time corresponding to two bits.
Reference numeral 20a denotes a phase comparator for detecting a phase difference between the output signal of the reproduction equalizer 4 and an output clock of a VCO (voltage controlled oscillator) 20c, which will be described hereinlater; 20b a loop filter for amplifying an, output of the phase comparator 20a, for returning the amplified output to the VCO 20c, and for obtaining predetermined PLL loop response characteristics; 20c the VCO for supplying a sampling clock to Viterbi decode a PR(1, 0, -1) signal and an operation clock of another circuit to the A/D converter 7.
The above phase comparator 20a, loop filter 20b, and VCO 20c construct the PLL circuit 20.
The operation will now be described.
The signal which was reproduced and was equalized by the reproduction equalizer 4 as mentioned above is outputted to the A/D converter 7 and phase comparator 20a.
In the PLL circuit 20, a phase difference between a clock generated by the VCO 20c and the output signal of the reproduction equalizer 4 is detected by the phase comparator 20a. The phase difference signal is inputted to the VCO 20c through the loop filter 20b, thereby performing a phase lock so that the phase difference is almost equal to 0. Frequency characteristics and a gain of the loop filter 20b, a sensitivity of the VCO 20c, and the like are set so that phase response characteristics of the PLL circuit can sufficiently absorb jitters which occur by a head tape system of the VTR and become hard to respond to various noises.
The PLL circuit is constructed as mentioned above and the phase of the lock of the PLL circuit is adjusted by, for example, adjusting the operation point of the phase comparator 20a or the like, so that a point at which an eye aperture becomes maximum can be sampled.
The equalized signal is sampled and digitized by the A/D converter 7 which is controlled by the clock generated by the PLL circuit. The digitized reproduced signal is delayed by the delay circuit 5 and is subtracted from the original signal by the subtracter 6. The integrated equalized waveform is converted to a waveform having PR(1, 0, -1) characteristics by the above operation and its eye-pattern has three values as shown in FIG. 8. Such a PR(1, 0, -1) signal is maximum likelihood decoded by the Viterbi decoder 8.
The combination of the PR(1, 0, -1) method and the Viterbi decoding is often used for a digital VTR using a high density magnetic recording or the like and can avoid bad low frequency band characteristics (S/N ratio, waveform distortion, and the like) of the magnetic recording system and can hold transmission errors minimum. Errors which occurred in the transmission path in the reproduced data decoded by the Viterbi decoder 8 are corrected by the error correction decoding circuit 10. The error corrected data is converted to the image signal of the original format by the reproduced signal processing circuit 11 and is converted to the analog image signal by the D/A converter 12 and is outputted as a reproduced image signal of the VTR. An output of the VCO 20c is also used as an operation clock of the circuits other than the A/D converter 7.
The conventional digital VTR is constructed as mentioned above. The reproduced eye-pattern of the equalizer output of the PR(1, -1) method shown in FIG. 5 has a waveform as shown in FIG. 9A. In such an eye-pattern, as shown in the diagram, a window width in the direction of the time base is narrower as compared with that of the integrating method in FIG. 4. In case of A/D converting, therefore, when the phase of the A/D conversion clock added to the A/D converter 7 from the PLL circuit 20 is deviated from the optimum position in FIG. 9B to a position as shown in FIG. 9C or 9D, there is a problem such that the reproduced errors rapidly increase.
In the conventional example, the apparatus is constructed in a manner such that a clock such as a sampling clock or the like of the A/D converter 7 is extracted from the analog signal which is generated from the reproduction equalizer 4 by the PLL circuit and the reproduced signal equalized by the reproduction equalizer 4 is sampled by the extracted clock. Generally, however, in the PLL circuit constructed in an analog manner, especially, in the case where a quality of the reproduced signal is low and the signal is reproduced at a high speed as in the digital VTR, there are problems such that it is difficult to hold a stability, it is necessary to adjust a sampling phase, and the like.